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IS61LV25616
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY
FEATURES
* High-speed access time: -- 7, 8, 10, 12, and 15 ns * CMOS low power operation * Low stand-by power: -- Less than 5 mA (typ.) CMOS stand-by * TTL compatible interface levels * Single 3.3V power supply * Fully static operation: no clock or refresh required * Three state outputs * Data control for upper and lower bytes * Industrial temperature available
ISSI
(R)
AUGUST 2000
DESCRIPTION The ISSI IS61LV25616 is a high-speed, 4,194,304-bit static
RAM organized as 262,144 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory.A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV25616 is packaged in the JEDEC standard 44-pin 400-mil SOJ, 44-pin TSOP Type II, 44-pin LQFP and 48-pin Mini BGA (8mm x 10mm).
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
256K x 16 MEMORY ARRAY
VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT
COLUMN I/O
CE OE WE UB LB
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2000, Integrated Silicon Solution, Inc.
CONTROL CIRCUIT
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/29/00
1
IS61LV25616
PIN CONFIGURATIONS 44-Pin TSOP (Type II) and SOJ 44-Pin LQFP
ISSI
(R)
A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A17 A16 A15 OE UB LB I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10
CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7
44 43 42 41 40 39 38 37 36 35 34 33 1 32 2 31 3 30 4 29 5 TOP VIEW 28 6 27 7 26 8 25 9 24 10 23 11 12 13 14 15 16 17 18 19 20 21 22 WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A17 A16 A15 A14 A13 A12 A11 A10 OE UB LB
I/O15 I/O14 I/O13 I/O12 GND Vcc I/O11 I/O10 I/O9 I/O8 NC
48-Pin mini BGA
1 2 3 4 5 6
PIN DESCRIPTIONS
A0-A17 I/O0-I/O15 CE OE WE LB UB NC Vcc GND Address Inputs Data Inputs/Outputs Chip Enable Input Output Enable Input Write Enable Input Lower-byte Control (I/O0-I/O7) Upper-byte Control (I/O8-I/O15) No Connection Power Ground
A B C D E F G H
LB I/O8 I/O9 GND Vcc I/O14 I/O15 NC
OE UB I/O10 I/O11 I/O12 I/O13 NC A8
A0 A3 A5 A17 NC A14 A12 A9
A1 A4 A6 A7 A16 A15 A13 A10
A2 CE I/O1 I/O3 I/O4 I/O5 WE A11
N/C I/O0 I/O2 Vcc GND I/O6 I/O7 NC
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/29/00
IS61LV25616
TRUTH TABLE
WE X H X H H H L L L CE H L L L L L L L L OE X H X L L L X X X LB X X H L H L L H L UB X X H H L L H L L I/O PIN I/O0-I/O7 I/O8-I/O15 High-Z High-Z High-Z DOUT High-Z DOUT DIN High-Z DIN High-Z High-Z High-Z High-Z DOUT DOUT High-Z DIN DIN
ISSI
Vcc Current ISB1, ISB2 ICC ICC
(R)
Mode Not Selected Output Disabled Read
1 2 3 4 5
Write
ICC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter VTERM TBIAS VCC TSTG PT Terminal Voltage with Respect to GND Temperature Under Bias Vcc Related to GND Storage Temperature Power Dissipation Value -0.5 to Vcc+0.5 -45 to +90 -0.3 to +4.0 -65 to +150 1.0 Unit V C V C W
6 7 8 9 10
Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C 7, 8, 10 ns VCC 3.3V +10%, -5% 3.3V +10%, -5% 12 ns, 15 ns VCC 3.3V 10% 3.3V 10%
11 12
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/29/00
3
IS61LV25616
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol VOH VOL VIH VIL ILI ILO Parameter Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage(1) Input Leakage Output Leakage GND VIN VCC GND VOUT VCC, 4 Outputs Disabled Com. Ind. Com. Ind. Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 -- 2.0 -0.3 -1 -5 -1 -5
ISSI
Max. -- 0.4 VCC + 0.3 0.8 1 5 1 5 Unit V V V V A A
(R)
Notes: 1. VIL (min.) = -2.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol ICC ISB Parameter Vcc Dynamic Operating Supply Current TTL Standby Current (TTL Inputs) TTL Standby Current (TTL Inputs) CMOS Standby Current (CMOS Inputs) Test Conditions VCC = Max., Com. IOUT = 0 mA, f = fMAX Ind. VCC = Max., VIN = VIH or VIL CE VIH, f = fMAX. VCC = Max., VIN = VIH or VIL CE VIH, f = 0 Com. Ind. Com. Ind. -7, -8 Min. Max. -- -- -- -- -- -- -- -- 260 300 85 95 20 25 10 15 -10 Min. Max. -- -- -- -- -- -- -- -- 260 300 85 95 20 25 10 15 -12 Min. Max. -- -- -- -- -- -- -- -- 240 280 75 85 20 25 10 15 -15 Min. Max. -- -- -- -- -- -- -- -- 220 250 65 75 20 25 10 15 Unit mA mA
ISB1
mA
ISB2
VCC = Max., Com. CE VCC - 0.2V, Ind. VIN VCC - 0.2V, or VIN 0.2V, f = 0
mA
Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. Shaded area product in development
CAPACITANCE(1)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
Note: 1. Tested initially and after any design or process changes that may affect these parameters.
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/29/00
IS61LV25616
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Read Cycle Time Address Access Time Output Hold Time CE Access Time OE Access Time OE to High-Z Output OE to Low-Z Output CE to High-Z Output CE to Low-Z Output LB, UB Access Time LB, UB to High-Z Output LB, UB to Low-Z Output Power Up Time Power Down Time -7 Min. Max. 7 -- 3 -- -- -- 0 0 2.5 -- 0 0 0 -- -- 7 -- 7 3.5 2.5 -- 3 -- 3 2.5 -- -- 7 -8 Min. Max. 8 -- 3 -- -- -- 0 -- 3 -- 0 0 0 -- -- 8 -- 8 3.5 3 -- 3 -- 3.5 3 -- -- 8 -10 Min. Max. 10 -- 3 -- -- -- 0 0 3 -- 0 0 0 -- -- 10 -- 10 4 4 -- 4 -- 4 3 -- -- 10 -12 Min. Max. 12 -- 3 -- -- -- 0 0 3 -- 0 0 0 -- -- 12 -- 12 5 5 -- 6 -- 5 4 -- -- 12
ISSI
-15 Min. Max. 15 -- 3 -- -- 0 0 0 3 -- 0 0 0 -- -- 15 -- 15 7 6 -- 8 -- 7 5 -- -- 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(R)
1 2 3 4 5 6 7
tRC tAA tOHA tACE tDOE tHZOE(2) tLZOE(2) tHZCE(2 tLZCE(2) tBA tHZB(2) tLZB(2) tPU tPD
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Shaded area product in development
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1 and 2
8 9 10
319
AC TEST LOADS
ZO = 50 OUTPUT
50 1.5V 30 pF Including jig and scope
3.3V
11
OUTPUT 5 pF Including jig and scope 353
12
Figure 1
Figure 2 5
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/29/00
IS61LV25616
AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE = OE = VIL, UB or LB = VIL)
t RC
ADDRESS
ISSI
(R)
t AA t OHA
DOUT
PREVIOUS DATA VALID
t OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
OE
tOHA
tDOE
CE
tHZOE
tLZOE tACE tLZCE tHZCE
LB, UB
DOUT
HIGH-Z
tLZB
tBA
tRC
DATA VALID
tHZB
VCC
Supply Current
tPU
50%
tPD
ICC
50%
ISB
UB_CEDR2.eps
Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB, or LB = VIL. 3. Address is valid prior to or coincident with CE LOW transition.
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/29/00
IS61LV25616
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
Symbol Parameter Write Cycle Time CE to Write End Address Setup Time to Write End Address Hold from Write End Address Setup Time LB, UB Valid to End of Write WE Pulse Width WE Pulse Width (OE = LOW) Data Setup to Write End Data Hold from Write End
(2)
ISSI
-7 Min. Max. 7 5 5 0 0 5 5 7 3.5 0 -- 2 -- -- -- -- -- -- -- -- -- -- 3 -- -8 Min. Max. 8 5.5 5.5 0 0 5.5 5.5 5 4 0 -- 2 -- -- -- -- -- -- -- -- -- -- 3.5 -- -10 Min. Max. 10 8 8 0 0 8 8 10 6 0 -- 2 -- -- -- -- -- -- -- -- -- -- 5 -- -12 Min. Max. 12 8 8 0 0 8 8 12 6 0 -- 2 -- -- -- -- -- -- -- -- -- -- 6 -- -15 Min. Max. 15 10 10 0 0 10 10 12 7 0 -- 2 -- -- -- -- -- -- -- -- -- -- 7 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns
(R)
1 2 3 4 5 6 7 8 9 10 11 12
tWC tSCE tAW tHA tSA tPWB tPWE1 tPWE2 tSD tHD tHZWE tLZWE
(2)
WE LOW to High-Z Output WE HIGH to Low-Z Output
Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured 500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. Shaded area product in development
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/29/00
7
IS61LV25616
AC WAVEFORMS WRITE CYCLE NO. 1 (CE Controlled, OE is HIGH or LOW) (1 )
t WC
ADDRESS
VALID ADDRESS
ISSI
(R)
t SA
CE
t SCE
t HA
WE
t AW t PWE1 t PWE2 t PBW
UB, LB
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t LZWE
t SD
DIN
t HD
DATAIN VALID
UB_CEWR1.eps
Notes: 1. WRITE is an internally generated signal asserted during an overlap of the LOW states on the CE and WE inputs and at least one of the LB and UB inputs being in the LOW state. 2. WRITE = (CE) [ (LB) = (UB) ] (WE).
8
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/29/00
IS61LV25616
AC WAVEFORMS WRITE CYCLE NO. 2 (WE Controlled. OE is HIGH During Write Cycle) (1,2)
t WC
ADDRESS
VALID ADDRESS
ISSI
(R)
1
t HA
2 3
OE
CE
LOW
t AW t PWE1
WE
t SA
UB, LB
t PBW
4
t LZWE
HIGH-Z
t HZWE
DOUT
DATA UNDEFINED
5
UB_CEWR2.eps
t SD
DIN
t HD
DATAIN VALID
6 7 8
WRITE CYCLE NO. 3 (WE Controlled. OE is LOW During Write Cycle) (1)
t WC
ADDRESS
VALID ADDRESS
OE CE
LOW
t HA
9
LOW
t AW t PWE2
WE
10 11
t LZWE
t SA
UB, LB
t PBW
t HZWE
DOUT
DATA UNDEFINED
HIGH-Z
t SD
DIN
t HD
12
UB_CEWR3.eps
DATAIN VALID
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/29/00
9
IS61LV25616
AC WAVEFORMS WRITE CYCLE NO. 4 (LB, UB Controlled, Back-to-Back Write) (1,3)
ISSI
(R)
t WC
ADDRESS
ADDRESS 1
t WC
ADDRESS 2
OE
t SA
CE
LOW
WE
t HA t SA t PBW t PBW
WORD 2
t HA
UB, LB
WORD 1
t HZWE
DOUT
HIGH-Z
t LZWE t HD
DATAIN VALID
DATA UNDEFINED
t SD
DIN
t SD
DATAIN VALID
t HD
UB_CEWR4.eps
Notes: 1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The t SA, t HA, t SD, and t HD timing is referenced to the rising or falling edge of the signal that terminates the Write. 2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state. 3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.
10
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/29/00
IS61LV25616
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed (ns) 7 Order Part No. IS61LV25616-7T IS61LV25616-7K IS61LV25616-7LQ IS61LV25616-7B IS61LV25616-8T IS61LV25616-8K IS61LV25616-8LQ IS61LV25616-8B IS61LV25616-10T IS61LV25616-10K IS61LV25616-10LQ IS61LV25616-10B IS61LV25616-12T IS61LV25616-12K IS61LV25616-12LQ IS61LV25616-12B IS61LV25616-15T IS61LV25616-15K IS61LV25616-15LQ IS61LV25616-15B Package TSOP (Type II) 400-mil SOJ LQFP Mini BGA (8mm x 10mm) TSOP (Type II) 400-mil SOJ LQFP Mini BGA (8mm x 10mm) TSOP (Type II) 400-mil SOJ LQFP Mini BGA (8mm x 10mm) TSOP (Type II) 400-mil SOJ LQFP Mini BGA (8mm x 10mm) TSOP (Type II) 400-mil SOJ LQFP Mini BGA (8mm x 10mm)
ISSI
Industrial Range: -40C to +85C
Speed (ns) 8 Order Part No. IS61LV25616-8TI IS61LV25616-8KI IS61LV25616-8LQI IS61LV25616-8BI IS61LV25616-10TI IS61LV25616-10KI IS61LV25616-10LQI IS61LV25616-10BI IS61LV25616-12TI IS61LV25616-12KI IS61LV25616-12LQI IS61LV25616-12BI IS61LV25616-15TI IS61LV25616-15KI IS61LV25616-15LQI IS61LV25616-15BI Package TSOP (Type II) 400-mil SOJ LQFP Mini BGA (8mm x 10mm) TSOP (Type II) 400-mil SOJ LQFP Mini BGA (8mm x 10mm) TSOP (Type II) 400-mil SOJ LQFP Mini BGA (8mm x 10mm) TSOP (Type II) 400-mil SOJ LQFP Mini BGA (8mm x 10mm)
(R)
1 2 3 4 5 6 7 8 9
8
10
10
12
12
15
15
Shaded area product in development
Shaded area product in development
ISSI
(R)
10 11 12
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com
Integrated Silicon Solution, Inc. -- 1-800-379-4774
Rev. B 09/29/00
11

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